As illustrated in example FIG. 1, a wire pad of a semiconductor device includes low-k layer 100, oxide layer 102, SiCN layer 104, nitride film 106, and TEOS film 108, which are sequentially formed to predetermined thicknesses. Layers 105a, 105b and 105c are formed between SiCN layer 104 and nitride film 106. Layers 107a and 107b are formed between nitride film 106 and TEOS film 108 while layer 109 is formed over TEOS film 108. Copper line 110 passing through the low-k layer 100 and SiCN layer 104 through a damascene process, and aluminum copper line 112 passing through nitride film 106 and TEOS film 108.
Example FIG. 2 illustrates a device for performing an EM/SM (Electro-migration/Stress-migration) test of a semiconductor device through the application of a force for a predetermined time. Semiconductor device 1 is located at one side of PCB 5, and includes pad ‘a’ which electrically connected to PCB 5 using wires 6. Semiconductor pad ‘a’ is electrically connected to wire 6 via contact ‘b.’ Wire portion ‘c’ electrically connects wire 6 at another end to pad ‘e’ of PCB 5 at contact ‘d.’
An EM/SM test of plural semiconductor devices 1 having eight pads was carried out was carried out by applying predetermined force to the points of action ‘f’ of the wire 6 for a predetermined test time. Table 1 illustrates the results of the EM/SM test of the semiconductor device 1.
TABLE 1DEK213 #03Wire #Tensile Strength of WirePKG ##01#02#03#04#05#06#07#08AVGC13#010.50.50.50.50.50.50.50.80.50C13#021.01.00.50.50.50.51.01.00.75C13#030.50.50.50.50.50.50.50.50.50C13#040.51.50.50.50.50.51.00.50.69C13#050.50.50.30.50.50.50.50.50.48C13#06x0.50.50.51.02.50.71.00.96C13#070.50.50.30.30.30.30.51.00.44C13#080.20.20.20.20.20.20.50.50.28C13#090.20.50.50.50.30.31.00.50.48C13#100.51.00.50.50.20.50.50.50.53C13#110.50.50.50.30.50.50.50.50.48C13#120.50.50.50.20.50.50.50.20.43C13#130.30.50.20.30.30.20.50.50.35C13#140.50.70.20.20.30.30.30.30.35C13#150.5.50.30.30.30.50.50.50.43C13#16xx0.30.30.30.30.50.30.33C13#170.30.50.50.30.30.30.30.30.35C13#180.30.50.30.30.50.50.50.50.43C13#190.50.50.20.30.20.30.50.50.38C13#200.70.70.50.30.30.51.01.00.63C13#210.50.50.20.30.20.30.50.50.38C13#220.50.50.30.30.20.20.3x0.33C13#230.20.20.20.30.30.30.50.50.31C13#240.50.50.50.20.20.20.30.30.34C13#250.50.50.30.30.30.32.50.50.65
As illustrated in Table 1, the EM/SM test ‘x’ denotes that the wire is not bounded in the regions (a) to (e) even when predetermined force is applied to the point (f) of action for a predetermined test time.
Accordingly, Table 1 shows that the wires 6 were easily bounded in the regions between ‘a’ to ‘e’, when a predetermined force, for example, approximately 0.5 g, is applied to the points ‘f’ of action of wire 6 in the EM/SM test.
Particularly, in situations of a semiconductor device using a Cu/low-k layer, the low-k layer has a low mechanical strength and a bonding force between the low-k layer. In turn, SiCN (or SiCON) layer, serving as a barrier layer, is weak. Accordingly, the semiconductor device may be deficient in terms of wire bounding in wire bonds.